I've designed a Switch Level Circuit Simulator which during the project of MOS transistor circuit networks allows to find logic errors in the designed architecture, before entering in the production phase. Programmed by C.
Download the documentation about the Switch Level Circuit Simulator:
calcolatori_elettronici_tesina.pdf
335kB
Copyright © 2003, 2008 Tarin Gamberini
Last updated 20/01/2008